1. Field of the Invention
The present invention relates to a large scale integrated (LSI) semiconductor device and, more particularly, relates to an improvement in a basic cell of a masterslice semiconductor device, such as a gate array, fabricated with a large number of transistors arranged along both row and column directions of a semiconductor substrate.
2. Description of the Related Art
Masterslice semiconductor technology can provide custom-tailored large scale integrated semiconductor devices at a low cost and in a short turnaround time. That is, a large number of transistors and resistors, which are formed in a semiconductor substrate ahead of time, are interconnected using masks having wiring patterns which allow the devices to meet each customer's specific functional requirements. In the masterslice semiconductor device, transistors are usually arranged in a number of unit groups called basic cells each having an identical pattern. An exemplary basic cell configuration and a circuit formed from the basic cells are disclosed in U.S. Pat. No. 4,412,1237 to Matsumura et al, issued Oct. 25, 1983.
FIG. 1 is a plan view of the general arrangement of a bulk pattern of a gate array. As illustrated in FIG. 1, on a semiconductor substrate chip 100, the basic cells BC are arranged in columns as basic cell arrays BL.sub.1, BL.sub.2, . . . BL.sub.n. Each of the basic cells BC is, in general, at least a pair of p-channel and n-channel MIS (Metal Insulator Semiconductor) transistors (which will be referred to as p-channel and n-channel transistors hereinafter). The column shaped basic cell arrays are arranged with a predetermined space therebetween. At the periphery of the chip 10, is a pad region which includes pads PD, each used as a terminal to an external circuit. An input/output region is set aside for input/output cells I/O, each including an input/output circuit. The space between each adjacent basic cell array is usually used for distributing wiring lines interconnecting the basic cells located in the same basic cell arrays or between basic cell arrays.
FIG. 2 is a plan view of a bulk pattern in a prior art basic cell. In FIG. 2, sources and drains of p-channel transistors QP1 and QP2 are formed in a p-type region 1, and sources and drains of the n-channel transistors QN1 and QN2 are formed in an n-type region 2. A polysilicon gate electrode 3G1, which extends along one of the gate channels in each p-type region 1 and n-type region 2, forms a single common gate for the p-channel transistor QP1 and n-channel transistor QN1, while the polysilicon gate electrode 3G2, which extends along another gate channel in each p-type region 1 and n-type region 2, forms a single common gate for the p-channel transistor QP2 and n-channel transistor QN2. P-type contact region 4CP and n-type contact region 4CN are used to keep all portions of the semiconductor substrate chip at a specified potential.
FIG. 3 is an equivalent circuit diagram of the circuit in the basic cell shown in FIG. 2. The basic cell is a pair of p-channel transistors QP1 and QP2, and a pair of n-channel transistors QN1 and QN2, each pair having a common gate.
A number of such basic cells, as illustated in FIGS. 2 and 3, are arranged in columns on a semiconductor chip, to form basic cell arrays, as illustrated in FIG. 1. The basic cells are interconnected using double-layer aluminum metallization technology, resulting in a desired LSI circuit network.
In the masterslice semiconductor device, the LSI circuit network is formed from a number of elementary circuit blocks, including 2-input NAND gates, 2-input NOR gates and/or flip-flop circuits as well as other elementary circuits. Each of the elementary circuits is created using a single or a plurality of the basic cells shown in FIGS. 2 and 3. The area occupied by the basic cells forming each elementary circuit is referred to as a unit cell. When some types of unit cells are produced, such as a RAM (Random Access Memory), a transmission gate circuit or a clocked gate circuit using the basic cells as shown in FIGS. 2 and 3, frequently one or more transistors in the basic cells are left unused. For example, conventionally, four of the basic cells, as shown in FIG. 2, are used to form a single 8-transistor RAM cell. However, only half of the total 16 transistors in the four basic cells are effectively utilized, and the other half of the transistors are left unused, inactive and, thus, wasted. With respect to a transmission gate circuit, two transmission gate circuits can be formed from one of the conventional basic cells, however, the circuits cannot operate independently, and, therefore, except in some special applications, one of the two transmission gates is frequently redundant. In a clocked gate circuit created using two basic cells, half of the eight transistors in the two conventional basic cells are left unused and inactive. The occurrence of the above-discussed redundant transistors reduces the integration density of the LSI circuit network on the masterslice semiconductor chip.